verilog problem 1

MnMWizard

Jan 31st, 2021

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`timescale 1ns / 1ps
//I changed the source node properties from Verilog to SystemVerilog so I could use arrays when creating inputs/outputs
module VerilogFile(input sw[15:0], output MOTOR, output ENA, output ENB, output LED[15:0]);
//Remember some sw[ ], atm 2 through 5, will not be used bc the ports will be linked to SWpos 0-3 in the master
assign ENA = sw[0];
assign LED[1] = sw[0];
assign LED[2] = sw[0]; //testing some stuff out
endmodule
// input [11:4] sw,
module PWM(
input clock,
input[3:0] SWpos, //this starts at SW2 since we're using sw[0] and sw[1] for etc.
output PWM //motor "power" signal
);
reg[9:0]counter;// 2^(num of bits) = 1024
reg[9:0]width;
reg PWMtemp;
initial begin
counter = 0;
width =0;
PWMtemp = 0;
end
always@(posedge clock)begin
if(counter == 1000) //resets the counter to 0 or increments
// if(counter == 16)
counter <= 0;
else
counter <= counter +1;
if(counter < width) begin
PWMtemp <= 1;
end
else begin
PWMtemp <=0;
end
end
//The above if/else sets the "power" to be on whenever counter is less
// than width. The value for width is set based on SWpos below.
always@(*)begin //not sure what * means as a sensitivity parameter but it works
case(SWpos)
//might add more cases later to account for sw[1] being an on/off switch
//Syntax is this - - - (in the case that SWpos is this):(set width = ___)
4'b0000:width = 10'd0;
4'b0001:width = 10'd250;
4'b0010:width = 10'd250;
4'b0100:width = 10'd250;
4'b1000:width = 10'd250;
4'b0011:width = 10'd500;
4'b0110:width = 10'd500;
4'b1100:width = 10'd500;
4'b0111:width = 10'd750;
4'b1110:width = 10'd750;
4'b1111:width = 10'd999;
default:width = 10'd0;
endcase
end
assign PWM = PWMtemp;
endmodule
/*
module disp(
input clk,
output reg [3:0] an, // 4 Digits on Basys 3 Board
output reg [6:0] seg // 7 Segment Display
);
// Use the 2 MSBs of 19-bit counter to create 190 Hz frequency refresh
reg [18:0] count;
always @ (posedge clk)
count = count + 1;
// This wire is driven by the 2 MSBs of the counter. We'll use it to
// refresh the display.
wire [1:0] refresh;
assign refresh = count[18:17];
// Usually always @ * is not recommended because it's resource intensive
// and usually unnecessary, and if you're not careful it will cause timing
// issues. This isn't an issue for a simple program like this though.
always @ (*)
if (SW1 = 0)
case(refresh)
2'b00:
begin
an = 4'b0111;
seg = 7'b0000111;
end
2'b01:
begin
an = 4'b1011;
seg = 7'0000111;
end
2'b10:
begin
an = 4'b1101;
seg = 7'b0000000;
end
2'b11:
begin
an = 4'b1110;
seg = 7'b0000000;
end
endcase
else case(refresh)
2'b00:
begin
an = 4'b0111;
seg = 7'b0000111;
end
2'b01:
begin
an = 4'b1011;
seg = 7'0000000;
end
2'b10:
begin
an = 4'b1101;
seg = 7'b0000000;
end
2'b11:
begin
an = 4'b1110;
seg = 7'b0000000;
end
endcase
*/