marcoshuck

Restador

Dec 15th, 2016
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VHDL 0.55 KB | None | 0 0
  1. library IEEE;
  2. use IEEE.STD_LOGIC_1164.ALL;
  3. use IEEE.STD_LOGIC_ARITH.ALL;
  4. use IEEE.STD_LOGIC_UNSIGNED.ALL;
  5.  
  6. entity base is
  7.     Port (
  8.         -- Entradas
  9.         A : in std_logic;
  10.         B : in std_logic;
  11.         Cin : in std_logic;
  12.         -- Salidas
  13.         R : out std_logic; -- Resultado de la resta
  14.         S : out std_logic; -- Signo
  15.         Cout : out std_logic; -- Acarreo
  16.         );
  17. end base;
  18.  
  19. architecture behavioral of base is
  20. begin
  21.     R<=((not(B) and Cin) or (not(A) and B and not(Cin)) or (A and not(B)));
  22.     Cout<=((A and B and Cin));
  23.     S<=((not(A) and B and not(Cin)));
  24. end behavioral;
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